17 Nov 2011

Engineer, Senior ASIC Design

Marvell – Posted by Hina KhanSanta Clara, CA, US

Job Description

Marvell require a “Engineer, Senior ASIC Design” in Santa Clara, CA:

BSEE with 7 years
MSEE with 5 years
Strong background on micro-architecture, verilog RTL logic design and module level verification
Familiar with synthesis…

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